Graphene chips are expected to continue Moore's Law


Material innovation has always been an important part of the semiconductor industry. In the past, the most important thing was the high-κ gate dielectric; now, cobalt is an important element in the replacement of tungsten in semiconductor middle-of-line (MOL) contacts.


Graphene, discovered in 2004, is by far the thinnest but most powerful material. It is an atomic layer of carbon that is 200 times more powerful than steel and is the thinnest material known to man - about 0.77 milligrams (mg) per square meter. It is also an ideal conductive and thermal conductor at room temperature.


Since graphene is an atomic layer, it is both soft and transparent. It also exhibits the ability to absorb light evenly in the visible and near-infrared spectrum, and is suitable for spintronic components.


Graphene will play an important role in its advanced packaging and interconnect materials for upcoming new semiconductor process nodes. In 3D IC packages, graphene can be used as a heat sink to reduce overall thermal resistance or as an EMI shield to reduce crosstalk.


The active graphene element layers can be stacked on each other via a low temperature conversion process (< 400 ° C) to realize a high density hetero-component that supports near-near-compute. This is currently an area that the US Department of Defense Advanced Planning Agency (DARPA) is currently actively researching and is part of its $1.5 billion electronic revitalization plan.


As for the interconnection, the kinetic energy of copper gradually disappears and becomes a major IC bottleneck, which is expected to reach a 40% delay at the 7 nm node. Graphene has a higher electron mobility and thermal conductivity, making it a more attractive interconnect material for semiconductor mid- and back-end processes, especially when the line width is < 30 nm.


Graphene-based semiconductor applications have begun to enter the market. At this year's World Mobile Communications Conference (MWC 2018) in Barcelona, a new optical transceiver incorporating graphene modulators and photodetectors was demonstrated to achieve speeds of up to 25 Gbits/s per channel. Nanomedical Diagnostics, a company based in San Diego, USA, has begun selling medical devices that use graphene biosensors. In Europe, Emberion is building a graphene photo-sensing device to improve the sensing capability in low-light conditions, and it is expected to find a place in the optical application.


The history of ion implantation technology is the best portrayal of how graphene is used in the semiconductor industry from basic scientific discovery to laboratory research to progress in plant manufacturing.


At the beginning of the development of ion implantation technology, the mainstream view of the semiconductor industry at the time was not optimistic that this technology was practical (relative to thermal diffusion), even if it could play a role, it only slightly increased the manufacturing output of existing products. From nuclear physics research transfer ion bombardment technology to semiconductor production is not obvious.


Later, Varian, led by British physicist Peter Rose, created a new advanced ion implant tool, which has been used by Texas DRAM maker Mostek to create a competitive MOS IC. The successful cooperation between Varian and Mostek is the turning point in the development of ion implants as a major semiconductor process.


In the following years, wafer companies introduced ion implantation techniques in more and more process steps. After about the 1970s, it gradually became one of the main processes used in semiconductor manufacturing.


Similarly, the graphene industry must work closely with the semiconductor industry to develop tools and technologies that overcome the challenges of graphene. Only in this way can we fully realize the future of including this 2D material.


The challenge of graphene involves the growth of materials with good uniformity over large areas. In addition, there are also problems to be solved in how to transfer graphene in a CMOS compatible manner and achieve high throughput.



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